By Topic

Enhancing microprocessor immunity to power supply noise with clock/data compensation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
T. Rahal-Arabi ; Logic Technol. Dev., Intel Corp., USA ; G. Taylor ; J. Barkatullah ; K. L. Wong
more authors

This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on a 130 nm processor demonstrate the approach.

Published in:

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

Date of Conference:

16-18 June 2005