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We developed a novel process to achieve ultra-thin gate dielectrics (EOT <0.7 nm) without involving nitrogen incorporation by engineering interface oxide thickness for sub 65nm high-performance logic technology node. Interfacial oxide formation was suppressed by the "oxygen-scavenging effect" using Hf metal on underlying HfO/sub 2/ device structure with appropriate annealing. The scavenging Hf metal layer consumes oxygen sources leading to further scaling still using undoped HfO/sub 2/. Using this fabrication approach, EOT of /spl sim/0.9 nm after conventional self-aligned MOSFET process was successfully obtained. In addition, further EOT improvement (EOT: 0.55-0.60nm) was realized in conjunction with nitrogen incorporation using scavenging effect.