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Highly cost effective and high performance 65nm S3 (stacked single-crystal Si) SRAM technology with 25F2, 0.16um2 cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications

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16 Author(s)
Soon-Moon Jung ; R&D Center, Samsung Electron., Kyungki-do, South Korea ; Youngseop Rah ; Taehong Ha ; Hanbyung Park
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In order to meet the great demands for higher density SRAM in all area of SRAM applications, the 25F2S3 (stacked single-crystal Si ) SRAM cell, which is a truly 3-dimensional device by stacking the load PMOS and the pass NMOS Tr. on the planar pull-down Tr., respectively in different levels, was developed and was reported in our previous study for low power applications. The previous reported S3 technology could not provide the high performance because it was developed for low power applications without salicide and high performance transistors. For the high performance transistor, the low thermal and low resistance processes are essential. In this study, the high performance CMOS transistors with 65nm gate length and l.6nm gate oxide, low resistance CVD Co for the small contact holes, and selectively formed CoSix in the peripheral area are added to the smallest 25F2 double stacked S3 SRAM cell for ultra high speed applications with the highest density such as 288M bits.

Published in:

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference:

14-16 June 2005