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Ultra-low standby power (U-LSTP) 65-nm node CMOS technology utilizing HfSiON dielectric and body-biasing scheme

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7 Author(s)
Kimizuka, N. ; Adv. Device Dev. Div., NEC Electron. Corp., Kanagawa, Japan ; Yasuda, Y. ; Iwamoto, T. ; Yamamoto, I.
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This paper reports 65-nm node ultra-low standby power CMOS technology for mobile applications, utilizing the combination of HfSiON FET and back-biasing scheme for the first time. With well-optimized channel, offset-spacer and halo conditions, physical gate length is successfully scaled down to 55 nm with excellent Vth roll-off and small DIBL, for both surface channel nFET and buried channel pFET. The record Ion/Ioff ratio, the drive current of 510/220 μA/μm with off-state leakage of 20/20 pA/μm, are obtained. We have also demonstrated body-biasing scheme feasibility for further subthreshold leakage (Isubth) reduction. By exploiting Fermi-level-pinning effect, we have reduced the channel doping concentration and suppressed gate induced drain leakage (IGIDL) even under reverse body-biasing condition. Total standby leakage (Isubth+IGIDL+Ig) are reduced to 1.4/0.32 pA/μm at Vdd= 0.8 V and Vb= ±1 V, which is the smallest value ever reported for 65nm-node LSTP.

Published in:

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference:

14-16 June 2005

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