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Control of process-induced damages in self-assembled porous silica/Cu damascene interconnects for 45nm node and beyond

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18 Author(s)
Yagi, R. ; MIRAI, National Inst. of Adv. Ind. Sci. & Technol., Ibaraki, Japan ; Chikaki, S. ; Shimoyama, M. ; Yoshino, T.
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New methods to recover process-induced damages of a self-assembled non-periodic porous silica (k=2.1) film were developed for Cu/low-k damascene interconnects for 45nm technology node and beyond. It is shown that process-induced damages can be suppressed by employing 1,3,5,7-tetra-methylcyclotetrasiloxane (TMCTS) vapor annealing after dry etching, by using a new suppressor for a Cu plating solution, and by post Cu-CMP cleaning with ethanol. Time-dependent dielectric breakdown lifetime of the non-periodic porous silica/Cu damascene was evaluated to be more than 10 years.

Published in:

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference:

14-16 June 2005