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The most suitable STI filling process has been developed for 45nm-node SoC platform. We found that the stress induced anti-isotropic impurity diffusion, which causes the Vth lowering. This novel phenomenon has been controlled by optimizing the SOD/HDP-CVD hybrid STI filling structure. At the same time, 20% drive current improvements of nFET and pFET have been obtained.
Date of Conference: 14-16 June 2005