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Stress controlled shallow trench isolation technology to suppress the novel anti-isotropic impurity diffusion for 45nm-node high-performance CMOSFETs

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21 Author(s)
Ota, K. ; Semicond. Solutions Network Co., Sony Corp., Kanagawa, Japan ; Yokoyama, T. ; Kawasaki, H. ; Moriya, M.
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The most suitable STI filling process has been developed for 45nm-node SoC platform. We found that the stress induced anti-isotropic impurity diffusion, which causes the Vth lowering. This novel phenomenon has been controlled by optimizing the SOD/HDP-CVD hybrid STI filling structure. At the same time, 20% drive current improvements of nFET and pFET have been obtained.

Published in:
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference: 14-16 June 2005

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