By Topic

Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

12 Author(s)
Byung Yong Choi ; Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea ; Park, Byung-Gook ; Yong Kyu Lee ; Suk Kang Sung
more authors

We present a 2-bit/cell SONOS memory transistor and investigate its scalability and reliability beyond 50nm NVM technology. This new memory, which is implemented by the damascene gate and our newly developed outer sidewall spacer processes, shows not only stable 2-bit operation but also high reliabilities (>105 endurance and good retention at 150°C) down to 80nm gate length that applies to next-generation NVM technology. In addition, dimensional effect (the lateral distance between two storage nodes) on the memory operation is reported to estimate the ultimate scaling limit of 2-bit/cell SONOS memory transistor.

Published in:

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference:

14-16 June 2005