By Topic

Low-cost modular testing and test resource partitioning for SOCs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Chakrabarty, K. ; Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA

The popularity of system-on-chip (SOC) integrated circuits has led to an unprecedented increase in test costs. This increase can be attributed to the difficulty of test access to embedded cores, long test development and test application times, and high test data volumes. A survey is presented of test resource partitioning techniques that facilitate low-cost SOC testing. Topics discussed include techniques for modular testing of digital, mixed-signal and hierarchical SOCs, as well as test data compression methods for intellectual property cores. Together, these techniques offer SOC integrators with the necessary means to manage test complexity and reduce test costs.

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:152 ,  Issue: 3 )