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Verification of timing performance in systems-on-chip (SoCs) is becoming more difficult as clock frequencies and levels of integration increase. As a result, on-chip timing measurement has become a very attractive alternative for validation of these systems because it helps to overcome the bandwidth and test access limitations inherent in SoC environments. Flash time-to-digital converters (TDCs) are well suited for use in on-chip timing measurement systems because they can be operated at high speeds, offer low test time and are relatively easy to integrate. However, clock jitter in modern SoCs is often of the same order of magnitude as the temporal resolution of the TDC itself. Therefore, techniques are required to increase TDC resolution while ensuring timing accuracy. A high-resolution flash TDC is presented that exploits the random offsets on flip-flops or arbiters to perform time quantisation. Also described is a novel technique based on additive temporal noise to accurately calibrate this measurement device. Simulation and experimental results reveal that the latter method can calibrate the high-resolution flash TDC down to 5 ps within reasonable error limits. In addition, accurate timing measurement of jitter below 10 ps has been experimentally validated using a high-resolution flash TDC fabricated in a 0.18-μm CMOS process.