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The high leakage current in the nanometre regime is becoming a significant proportion of power dissipation in CMOS circuits as threshold voltage, channel length and gate oxide thickness are scaled. Consequently, the identification and estimation of different leakage currents are very important in designing low power circuits. In the paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modelling of the different leakage currents in nanoscaled bulk CMOS devices is demonstrated. Different leakage currents are modelled based on the device geometry, 2-D doping profile and operating temperature. A circuit level model of subthreshold, junction band-to-band tunnelling (BTBT) and gate leakage is described. The presented model includes the impact of quantum mechanical behaviour of substrate electrons on the circuit leakage. Using the compact current model, a transistor has been modelled as a sum of current sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25 nm effective length) at room and elevated temperatures.