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A time-interleaved recursive loop band-pass delta-sigma modulator for a digital IF CDMA receiver

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3 Author(s)
Minho Kwon ; Electr. & Electron. Eng. Dept., Univ. of Yonsei, Seoul, South Korea ; Jungyoon Lee ; Gunhee Han

A bandpass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) recursive loop BPDSM architecture that consists of five-stage TI blocks for a code-division multiple-access (CDMA) receiver. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of the conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-μm CMOS process. The measured peak SNR for a 1.25-MHz bandwidth is 48 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm2.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:52 ,  Issue: 7 )