Skip to Main Content
A low-power, high-speed architecture which performs two-dimension forward and inverse discrete wavelet transform (DWT) for the set of filters in JPEG2000 is proposed by using a line-based and lifting scheme. It consists of one row processor and one column processor each of which contains four sub-filters. And the row processor which is time-multiplexed performs in parallel with the column processor. Optimized shift-add operations are substituted for multiplications, and edge extension is implemented by an embedded circuit. The whole architecture which is optimized in the pipeline design way to speed up and achieve higher hardware utilization has been demonstrated in FPGA. Two pixels per clock cycle can be encoded at 100 MHz. The architecture can he used as a compact and independent IP core for JPEG2000 VLSI implementation and various real-time image/video applications.