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An improved test access mechanism structure and optimization technique in system-on-chip

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4 Author(s)
Feng Jianhua ; Dept. of Microelectron., Peking Univ., Beijing, China ; Long Jieyi ; Xu Wenhua ; Ye Hongfei

This paper presents a new test access mechanism (TAM) architecture and optimization method based on an improved flexible-width test bus. The method is first to set up the test time lower bound that is not depends on TAM architecture, then to construct a bus assignment that makes test time up to the lower bound. We present experimental results on our improved flexible-width test buses for four benchmark SOCs. Experiment results in a significant reduction of the test time, and is better than the proposed traditional methods in test time.

Published in:

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.  (Volume:2 )

Date of Conference:

18-21 Jan. 2005