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Reducing leakage power in instruction cache using WDC for embedded processors

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2 Author(s)
Xin Lu ; Sch. of Microelectron., Shanghai Jiao Tong Univ., China ; Yuzhuo Fu

Power consumption is an important design issue of current embedded systems and SoC. It has been shown that instruction cache accounts for a significant portion of the power dissipation of the whole processor chip. WDC (way-decay cache) proposed in this paper is a novel cache architecture with resizable associativity and low leakage power. Experiment results show that for the SPECint95 benchmarks, WDC reduces energy consumption without significantly hindering performance.

Published in:

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific  (Volume:2 )

Date of Conference:

18-21 Jan. 2005