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Power consumption is an important design issue of current embedded systems and SoC. It has been shown that instruction cache accounts for a significant portion of the power dissipation of the whole processor chip. WDC (way-decay cache) proposed in this paper is a novel cache architecture with resizable associativity and low leakage power. Experiment results show that for the SPECint95 benchmarks, WDC reduces energy consumption without significantly hindering performance.