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Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

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2 Author(s)
Jeng-Liang Tsai ; Dept. of Electr. & Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA ; Chen, C.C.-P.

Zero-skew clock-tree with minimum clock-delay is preferable due to its low unintentional and process-variation induced skews. We propose a zero-skew buffered clock-tree synthesis flow and a novel algorithm that enables clock-tree optimization throughout the full zero-skew design-space by considering simultaneous buffer-insertion, buffer-sizing, and wire-sizing. For an industrial clock-tree with 3101 sink nodes, our algorithm achieves up to 45X clock-delay improvement and up to 23% power reduction compared with its initial routing.

Published in:

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific  (Volume:2 )

Date of Conference:

18-21 Jan. 2005