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An LP-based methodology for improved timing-driven placement

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3 Author(s)
Qingzhou Ben Wang ; Dept. of Comput. Sci., Univ. of Illinois at Chicago, IL, USA ; Lillis, J. ; Sanyal, S.

A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formulation captures all topological paths in a linear sized LP and thus, heuristic net weights or net budgets are not necessary. Additionally, explicit enumeration of a large number of paths is avoided. The flow begins with a given placement and iteratively extracts timing-critical sub-circuits, optimally places the sub-circuit by LP and applies a timing-driven legalizer. The approach is applied to the FPGA domain and yields an average of 19.6% reduction in clock period of routed MCNC designs versus I.6J (with reductions up to 39.5%).

Published in:

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific  (Volume:2 )

Date of Conference:

18-21 Jan. 2005