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Efficient synthesis of speed-independent combinational logic circuits

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2 Author(s)
Toms, W.B. ; Dept. of Comput. Sci., Manchester Univ., UK ; Edwards, D.A.

Speed-independent synthesis of combinational logic datapath circuits using tools such as Petrify is often inefficient or infeasible because such circuits typically contain many concurrent inputs and independent outputs. This paper presents a practical method for generating arbitrary combinational logic circuits, using a sub-class of speed-independent circuits known as Strongly-Indicating circuits, without the need to verify the speed-independence of the implementation through construction of a state-graph or other method.

Published in:

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific  (Volume:2 )

Date of Conference:

18-21 Jan. 2005