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Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms

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3 Author(s)
Zhe Ma ; IMEC/DESICS, Leuven, Belgium ; Catthoor, F. ; Vounckx, J.

Nowadays, the system-on-a-chip (SoC) has integrated more processors onto a single chip. Applications are also consisting of multiple (sub) tasks that are presented as different source code which can be partly executed concurrently. However, the subtask-level parallelism inside a single task is often too limited to fully utilize all the parallel processors and results in many slacks on processors. To better use the processors, subtasks of multiple tasks will have to be executed in an interleaving fashion. This paper proposes design-time algorithms to interleave subtasks based on the separated schedules of tasks. This interleaver can be considered as part of a hierarchical scheduler to steer the code generation of very complex applications with many tasks. The scheduling experiments show that the execution time can be shortened by 20%-30% when interleaving two tasks against the sequential execution without subtask interleaving. Moreover, the differences between the solutions given by our scheduling algorithm and the optimal solutions are less than 6% for up to 20 subtasks.

Published in:

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific  (Volume:2 )

Date of Conference:

18-21 Jan. 2005

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