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Design of an efficient memory subsystem for network processor

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5 Author(s)
Shuguang Gong ; Inst. of Comput. Technol. Graduate Sch., Chinese Acad. of Sci., Beijing, China ; Huawei Li ; Yufeng Xu ; Tong Liu
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The rapid growth of backbone network traffic increases the gaps among the available network bandwidth, the CPU computation power and the memory bandwidth. The memory bandwidth has become the main performance bottleneck of network processor. In this paper, an efficient memory subsystem design is proposed which combines dynamic memory allocation and a novel page-based memory access algorithm. The dynamic memory allocation achieves fast random packet access and flexible queue management. Utilizing the paged-based memory access algorithm, an efficient design of memory controller is proposed and high throughput can be implemented in the network processor.

Published in:

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.  (Volume:2 )

Date of Conference:

18-21 Jan. 2005