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Automated throughput-driven synthesis of bus-based communication architectures

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3 Author(s)
Pasricha, S. ; Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA ; Dutt, N. ; Ben-Romdhane, M.

As system-on-chip (SoC) designs become more complex, it becomes increasingly harder to design communication architectures which satisfy design constraints. Manually traversing the vast communication design space for constraint-driven synthesis is not feasible any more. In this paper we propose an approach that automates the synthesis of bus-based communication architectures for systems characterized by (possibly several) throughput constraints. Our approach accurately and effectively prunes the large communication design space to synthesize a feasible low-cost bus architecture which satisfies the constraints in a design.

Published in:

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific  (Volume:1 )

Date of Conference:

18-21 Jan. 2005