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Design and test of a scalable security processor

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5 Author(s)
Chih-Pin Su ; Dept. of Electr. Eng., National Tsing Hua Univ., Hsinchu, Taiwan ; Chen-Hsing Wang ; Kuo-Liang Cheng ; Chih-Tsun Huang
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This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology. The core area is 3.899mm × 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.

Published in:

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.  (Volume:1 )

Date of Conference:

18-21 Jan. 2005