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Low-power techniques for network security processors

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6 Author(s)
Yi-Ping You ; Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chun-Yen Tseng ; Yu-Hui Huang ; Po-Chiun Huang
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In this paper, we present several techniques for low-power design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.

Published in:

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific  (Volume:1 )

Date of Conference:

18-21 Jan. 2005