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ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress

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4 Author(s)
Rouying Zhan ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA ; Haolu Xie ; Haigang Feng ; Albert Wang

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at the full chip level. This paper reports a new CAD tool, entitled ESDZapper, to simulate the complex ESD protection zapping test procedures and to find the critical discharging path under a specific ESD stress. ESDZapper is developed based on a novel concept of ESD-critical parameters. Capability of the new tool is demonstrated using a practical design example in a 0.35μm BiCMOS technology.

Published in:

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific  (Volume:1 )

Date of Conference:

18-21 Jan. 2005