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A low power pipelined analog-to-digital converter using series sampling capacitors

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4 Author(s)
SeongHwan Cho ; Korea Adv. Inst. of Sci. & Technol., Daejon, South Korea ; Sungmin Ock ; Sang-Hoon Lee ; Joon-Suk Lee

A low power pipelined analog-to-digital converter (ADC) that employs sampling capacitors connected in series is presented. The series sampling capacitors minimize the size of the sampling capacitors to the kT/C limit without degrading the ADC's performance due to mismatch. Using this technique, a 10-bit 100 MHz pipelined ADC is designed and simulated. The ADC achieves 60 dB of signal-to-noise-and-distortion ratio (SNDR) at 100 MHz while consuming 47 mW from 1.8-V supply in 0.18 μm CMOS technology.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005