Skip to Main Content
A low power pipelined analog-to-digital converter (ADC) that employs sampling capacitors connected in series is presented. The series sampling capacitors minimize the size of the sampling capacitors to the kT/C limit without degrading the ADC's performance due to mismatch. Using this technique, a 10-bit 100 MHz pipelined ADC is designed and simulated. The ADC achieves 60 dB of signal-to-noise-and-distortion ratio (SNDR) at 100 MHz while consuming 47 mW from 1.8-V supply in 0.18 μm CMOS technology.