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An advanced design methodology for 90 nm and below system LSI is described. The methodology provides the total solution to solve timing closure, signal integrity issues and design for manufacturing in RTL to GDS2 silicon implementation. It also focuses on hierarchical and low power design implementation. Sign-off criteria to guarantee the first silicon success are presented. Also, the methodology is adapted for actual CPU RISC core design in 90 nm process technology, and the first silicon worked well as designed.