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A new switched capacitor (SC) circuit for image processing is presented. Optimized area occupancy and power consumption allow the integration of the proposed circuit into each pixel, in order to implement high speed pixel-parallel processing. The operation performed by the circuit consists of the accumulation of the absolute value of the difference between two voltage inputs, which is the base of a large set of image processing algorithms. Two circuit configurations have been developed and compared in this paper: a basic implementation and a second improved solution with higher sensitivity and linearity over the full output range. The improved pixel consists of 10 transistors and 3 capacitances and provides an output voltage range of 1.8 V with 3.3 V power supply. A test chip was fabricated in a 0.35 μm double-poly triple-metal CMOS process. The resulting 35 μm square pixel has a power consumption of 3 μW @ 3.3 V. The single absolute difference and accumulation is executed in 2 μs, which turns into a computing figure of 1.2 GOPS/mm2 and 1.3 TOPS/W.