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Reconfigurable multiple scan-chains for reducing test application time of SOCs

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3 Author(s)
Jiann-Chyi Rau ; Dept. of Electr. Eng., Tamkang Univ., Taipei Hsien, Taiwan ; Chih-Lung Chien ; Jia-Shing Ma

We propose an algorithm, based on a framework of reconfigurable multiple scan-chains for a system-on-chip, to minimize test application time. For the framework, the control signal combination causes the computing time to increase exponentially. The algorithm we propose introduces a heuristic control signal selection method to solve this problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan-chains. It could show significant reductions in test application times and computing times.

Published in:

2005 IEEE International Symposium on Circuits and Systems

Date of Conference:

23-26 May 2005