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The Ridgelet transform was recently introduced to overcome the weakness of wavelets in higher dimensions. In this paper, we present the design and FPGA implementation of the finite Ridgelet transform (FRIT) for image processing applications. The proposed architecture uses the finite Radon transform (FRAT) and 1D discrete biorthogonal wavelet transform (DBWT) as building blocks. A detailed evaluation of the FPGA implementation for the proposed architectures targeting the Xilinx Virtex-II device family has been reported, based on maximum system frequency, chip area and image size. The implementation results show that the core speed for the proposed FRIT architecture is around 100 MHz and it occupies 491 slices for an input image size of 7×7.