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Digital VLSI OFDM transceiver architecture for wireless SoC design

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3 Author(s)
Wei-Hsiang Tseng ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Ching-Chi Chang ; Chorng-Kuang Wang

This paper presents the VLSI architecture of an OFDM baseband transceiver for wireless communications. The open/closed-loop carrier recovery achieves the stepping frequency acquisition for high-band RF systems, and the proposed timing recovery cooperating with the self-correcting interpolation realizes an OFDM baseband digital IP design. Hardware sharing and power-of-2 coefficients fulfill this compact transceiver system chip. Simulations show that the receiver can deliver 10% packet error rate (PER) requirement under all specified SNR for IEEE 802.11a. Using the typical 0.25 micrometre CMOS technology, the chip occupies 3.5×3.5 mm2 area and consumes 109 mW under 2.5 V power supply.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005