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Rewiring algorithms provide a new style of logic transformations by replacing a target wire with its alternative wire while maintaining the functionality of the circuit. In this paper, these algorithms are used to minimize the number of LUTs used to map a given circuit with Flowmap. The proposed approach is to evaluate each alternative wire with Flowmap and choose the first one which can reduce the number of LUTs by 1 or more. Despite its simplicity, it can efficiently transform the circuit to one suitable to be mapped with Flowmap and used in FPGA. Experimental result shows that the proposed approach can reduce up to 17% of the LUTs in a circuit without any depth increment.