By Topic

Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Bo Hu ; Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA ; Zhao Li ; Lili Zhou ; Shi, C.-J.R.
more authors

A new, efficient, and reliable approach to speeding up large-scale mixed signal circuit simulation is proposed for full-chip electrical statistical analysis. This approach has been verified with an industry 4 GHz/6-bit ADC/DAC/DEMUX ASIC design. The key idea is to retain at the transistor level those devices that need to be modelled statistically and their surrounding circuitry and to replace the other parts of the circuit by analog behavioral models. Instead of using unproven VHDL-AMS or Verilog-A simulators not optimized for statistical electrical analysis, a state-of-the-art model compiler, MCAST, is used to compile analog behavioral models automatically into a designer's preferred circuit simulator. With the model compiler, digital and analog circuits at the behavioral level can be simulated efficiently and seamlessly with analog circuits at the transistor level by a SPICE-like circuit simulator. In this way, full-chip mixed-signal circuit simulation is orders of magnitude faster than that at the transistor level. Further, the simulation accuracy is kept as close to that of transistor-level simulation as possible. This approach has been applied successfully to dynamic nonlinearity analysis of the ADC/DAC/DEMUX ASIC caused by device mismatching due to process variations, which was previously an extremely time consuming task.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005