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Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique

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3 Author(s)
Olivieri, N. ; Dept. of Electron. Eng., La Sapienza Univ., Rome, Italy ; Scarana, M. ; Smorfa, S.

This work presents an analysis of power efficiency in microprocessor architectures targeting wide-range digital signal processing (DSP) applications. We defined a circuit level power estimation technique based on the integration of traditional analytical power models so as to account for both block-internal and interconnects-dependent dissipation and we extended it to provide applicability to specific DSP-related structures. We applied the modeling approach to several architecture schemes and demonstrated that a relatively novel solution, namely the transfer triggered architecture, can be the most power-efficient scheme in DSP applications.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005