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A novel and effective test circuit to measure cell-to-cell delay mismatch due to process variations is presented. A fully digital control circuit that efficiently realizes the technique is also described. The proposed test structure is realized by a series of modified ring oscillators that minimize factors of inaccuracy. The results of a simulation using 0.18 μm CMOS technology show the feasibility of the technique. This test structure can be beneficial in thoroughly characterizing the effects of systematical process variations inside the chip.