A low-power distributed wide-band LNA in 0.18 /spl mu/m CMOS

The implementation of low noise amplifier (LNA) front-ends is one of the challenging aspects in emerging ultra wide-band (UWB) radio frequency (RF) systems. In this paper, we propose a figure of merit (FOM) that captures the tradeoffs among linearity, noise figure (NF), power dissipation and utilization of raw technology speed. Different distributed amplifier (DA) architectures with a 10 dB pass band gain and 10 GHz bandwidth are designed and simulated in 0.18 /spl mu/m CMOS technology. The power consumption is reduced by using a Z/sub 0/ higher than the conventional 50 /spl Omega/, resulting in a four-section cascode DA that dissipates 12 mW from a single 1.8-V power supply. The NF and the output-referred 1-dB compression point at 5 GHz are 3.15 and 2.7 dBm.