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Fully-differential 13 Gbps clock recovery circuit for OC-255 SONET applications

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2 Author(s)
Wen Tsern Ho ; Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada ; M. N. El-Gamal

A fully differential, quasi-mixer based, half-rate clock recovery PLL has been implemented in a 0.18-μm CMOS technology, and is optimized for high-speed of operation at 13 Gbit/s. A special differential varactor tuning arrangement is used to provide a wide operating frequency range from 6.2 GHz to 7.2 GHz, with a power consumption of 69 mW.

Published in:

2005 IEEE International Symposium on Circuits and Systems

Date of Conference:

23-26 May 2005