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A low power block-matching analog motion estimation processor

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2 Author(s)
Panovic, M. ; Dept. of Electron. & Electr. Eng., Univ. Coll. London, UK ; Demosthenous, A.

This paper presents an analog motion estimation processor utilizing the full-search block-matching algorithm for portable video applications. The system features digital I/O and a low power, area efficient analog computation core. The proof-of-concept processor was fabricated in 0.8μm CMOS occupying 0.63 mm2, and operates on 4-by-4 pixel blocks and a search window of 8-by-8 pixels. Its architecture is however readily scalable to larger pixel blocks and more advanced technologies. Measured results for QCIF video sequences show excellent PSNR performance. A comparison with all-digital equivalents is presented, showing the superiority of the analog approach in all relevant metrics.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005