By Topic

VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Jen-Shiun Chiang ; Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan ; Chih-Hsien Hsia ; Hsin-Jung Chen ; Te-Jung Lo

The paper presents a low memory and high speed VLSI architecture for 2D lifting-based lossless 5/3 filter discrete wavelet transform (DWT). The architecture is based on the proposed interlaced read scan algorithm (IRSA) and parallel scheme processing to achieve low memory size and high speed operation. The proposed lifting-based DWT architecture has the advantages of lower computational complexity, transforming signal with extension, and regular data flow, and is suitable for VLSI implementation. It can be applied to real time image/video operation of JPEG2000 and MPEG-4 applications. Basing on the proposed architecture, we designed and simulated a 2D DWT VLSI chip by 0.35 μm 1P4M CMOS technology. The memory requirement of the N×N 2D DWT is N, and it can operate at 100 MHz clock frequency.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005