By Topic

An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kuan-Hung Chen ; Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chia-Yi, Taiwan ; Jiun-In Guo ; Jinn-Shyan Wang

This paper proposes an efficient direct 2D transform coding IP design for MPEG-4 AVC/H.264. The proposed direct 2D transform coding design eliminates the data transposition registers to greatly increase the data processing rate and reduce the hardware cost. When comparing the proposed design with the existing designs, the proposed design has over 90% higher hardware efficiency through the measure of DTUA (data throughput per unit area) for computing the multi-transform in MPEG-4 AVC/H.264. By using a 0.18-μm CMOS technology, the optimum operating clock frequency of the proposed multi-transform design is 100 MHz, which achieves 800 Mpixels/sec data throughput rate with an area cost of 6482 gates. Moreover, the proposed design balances the I/O data rate and processing rate through an interlaced I/O schedule.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005