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The carry-select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However, the conventional carry-select adder (CSL) is still area-consuming due to the dual ripple-carry adder structure. The excessive area overhead makes CSL relatively unattractive but this has been circumvented by the use of an add-one circuit introduced recently. In this paper, an area efficient square root CSL scheme based on a new first zero detection logic is proposed. The proposed CSL witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique. For 64-bit addition, our proposed CSL requires 44% fewer transistors than the conventional one. Simulation results indicate that our proposed CSL can complete 64-bit addition in 1.50 ns and dissipate only 0.35 mW at 1.8V in TSMC 0.18 μm CMOS technology.
Date of Conference: 23-26 May 2005