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A 1.5V 10-b 4MS/s pipeline ADC for sensor interfacing is described. Amplifiers are efficiently shared between stages and low-voltage techniques are used to reduce the power supply down to 1.4V. The selected resolution-per-stage greatly simplifies the implementation of a low-power design. Simulated results using a standard digital 0.18 μm CMOS technology exhibit 9.5 effective bits at Nyquist-rate. The chip occupies 0.6 mm2 and dissipates only 3 mW at maximum conversion-rate.