This paper introduces a one-quadrant discrete-time cellular neural network architecture for the pixel-level snakes, an active-contour-based technique. The motivation behind such an architecture is to have a subsequent on-chip implementation with better figures of merit, especially area consumption and processing speed. The current paper goes through the B/W operations performed in the pixel-level snake algorithm.
Published in:
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Date of Conference: 23-26 May 2005