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Accurate analysis of VLSI interconnects is essential to the performance-driven synthesis and layout of integrated circuits. Existing techniques are based on either simulation, analytic formulas, or small-scale table lookup. There are tradeoffs in compute time and accuracy. In this paper, we present an effective approach which captures the accuracy of SPICE while remaining close to Elmore delay in terms of computational overhead. Our method is based on topology indexed lookup tables (TILT), and uses a extremely large database of precomputed values.
Date of Conference: 23-26 May 2005