By Topic

A countermeasure against differential power analysis based on random delay insertion

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Bucci, M. ; Infineon Technol. AG, Graz, Austria ; Luzzi, R. ; Guglielmo, M. ; Trifiletti, A.

Differential power analysis is widely recognized as an extremely powerful and low-cost technique to extract secret information from cryptographic devices. As a consequence, DPA-countermeasures have been proposed in the technical literature ranging over every abstraction level in an embedded system, from software to transistor-level techniques. In this paper, a novel gate-level countermeasure is proposed which, exploiting the insertion of random delays in the datapath of a cryptographic processor, allows us to randomize not just the instantaneous current consumption profile but also the total charge quantity transferred from the power supply during a clock cycle.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005