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Hierarchical instruction encoding for VLIW digital signal processors

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9 Author(s)
Chia-Hsien Liu ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Taiwan ; Tay-Jyi Lin ; Chie-Min Chao ; Pi-Chen Hsiao
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VLIW-based architectures are very popular in high-performance DSPs, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixed-length instruction encoding, (2) NOP insertion due to limited parallelism, (3) repetitive codes for loop unrolling. The paper describes a novel hierarchical instruction encoding that addresses these three problems in order to improve the VLIW code density. In simulations, the proposed encoding scheme saves 61.4-66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP. The prototype is implemented in 0.18 μm CMOS technology with its operating frequency at 208 MHz.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005

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