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An area-efficient and protected network interface for processing-in-memory systems

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4 Author(s)
Mediratta, S.D. ; Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA ; Steele, C. ; Sondeen, J. ; Draper, J.

This paper describes the implementation of an area-efficient and protected user memory-mapped network interface, the pbuf (parcel buffer), for the data intensive architecture (DIVA) processing-in-memory (PIM) system. This implementation of the pbuf in TSMC 0.18 μm CMOS technology displays an aggregate bi-directional throughput of 48.08 Gbps, using low area (0.56 mm2) and power consumption (32.30 mW). These characteristics, especially the low area and power, have made the current implementation an ideal choice for assimilation in DIVA PIM systems, since low area and power are critical design requirements in the PIM philosophy. The pbuf implementation has been verified by the execution of a 2-PIM transitive closure benchmark at 140 MHz on an HP Itanium2-based Long's Peak server containing DIMMs populated with DIVA-H PIM chips.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005