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MOS current-mode logic (MCML) is an appealing design style for high-speed circuit applications. The article introduces a method to design MCML circuits optimally using a mathematical programming approach. The technique may be used to achieve a variety of design goals, such as minimum delay, minimum power consumption, and minimum power-delay product (PDP). A by-product of this technique is that it provides an acceptable estimation of various design figures, like delay, power dissipation, voltage swing, and DC bias values. We apply the technique to the design of two different topologies for MCML universal gates tuned for minimum delay and minimum PDP. Simulation results confirm the accuracy of the design with average error of 8.3% in calculated results. Both circuits are implemented in a standard 0.18 μm CMOS technology.
Date of Conference: 23-26 May 2005