By Topic

On the impact of traffic statistics on quality of service for networks on chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Santi, S. ; ARCES, Bologna Univ., Italy ; Bill Lin ; Kocarev, L. ; Maggio, G.M.
more authors

Packet switched networks on chip (NoC) architectures have been proposed as a solution to the global interconnect problem in the nanoscale systems on chip (SoC) design era. An important design consideration for NoC, is silicon cost. Towards the goal of keeping the NoC simple, we pose the following question: under what traffic conditions will quality of service (QoS) be provided without the added complexity of an explicit QoS mechanism? In this paper, we take the first step towards answering this question by empirically analyzing different combinations of traffic patterns and injection processes. Specifically, we analyze the effects of different traffic on latency under two cases: (1) an NoC with no QoS mechanism (i.e. without distinction among different classes of service); and (2) an NoC with the simplest distinction into two classes of service: guaranteed service and best effort.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005