Skip to Main Content
The functional characteristics and design challenges associated with the different building blocks of a CMOS front-end architecture for hard disk drive read-channel equalizer are presented. These include the mixed-signal design of a variable gain amplifier, a continuous-time low-pass filter, data converters and clock generation and recovery circuits. With a realistic computer model of the system, the analysis of structural variations and effects of component nonidealities becomes feasible. Numerical results show that circuit techniques that minimize sensitivity to power-supply and substrate noise, while maintaining the power dissipation and parameter tuning range are critical.