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A memory-efficient architecture design for a de-blocking filter in H.264/AVC is presented. We use the novel column-of-pixel data arrangement to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared with some existing approaches of realizing the de-blocking filter, the proposed design saves about one-half of the processing cycles. With the novel data arrangement and hybrid filter scheduling, an efficient architecture design is implemented. Further, it is evaluated on an H.264 system and easily achieved real-time decoding with 1080 HD (1920×1088 @ 30 fps) when the working frequency is 100 MHz.