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Wire-driven microarchitectural design space exploration

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4 Author(s)
Ekpanyapong, M. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Sung Kyu Lim ; Chinnakrishnan Ballapuram ; Lee, H.-H.S.

We propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. At the heart of our framework, named AMPLE (adaptive microarchitectural planning engine), are wire delay-driven microarchitectural floorplanning and adaptive parameter tuning schemes that address interconnect issues with high exploration efficiency and accuracy. Our framework significantly outperforms the commonly used brute-force and simulated annealing methods in terms of exploration time efficiency as well as the performance and area quality for a large design space.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005